Director, Silicon Logical Design
Lead and scale Graphcore's Logical Design group within the Silicon department, owning strategy, technical direction, execution quality, and team development for microarchitecture and RTL design efforts.
Responsibilities
- Define and execute the strategic roadmap for Logical Design aligned with silicon and product strategy
- Lead, grow and mentor a high-performing RTL and microarchitecture design organisation
- Establish and implement best-in-class design methodologies, documentation standards and quality metrics
- Drive continuous improvement across team structure, workflows, tooling and design processes
- Provide technical oversight of microarchitecture specification and RTL development across major blocks and subsystems
- Guide architectural feasibility studies and contribute to architectural trade-offs and microarchitecture definition
- Oversee integration of third-party IP, complex application-specific blocks and high-performance custom designs
- Ensure robust design sign-off through linting, synthesis, CDC/RDC, timing closure and coverage metrics
- Partner with Physical Design, Verification, DFT, Architecture and Program Management teams
- Foster communication across teams and global sites
- Support silicon bring-up and debug with expert guidance on RTL behaviour and architecture
- Own delivery of high-quality, on-schedule RTL for multiple parallel silicon programs
- Establish project planning and tracking practices including resource planning and risk mitigation
- Champion design automation and infrastructure improvements
Requirements
- Degree in Computer Science, Electrical Engineering or a related field; advanced degree preferred
- Extensive experience in digital logical design, microarchitecture and RTL development for large-scale, high-performance silicon projects
- Proven success leading and developing technical teams in a semiconductor environment
- Deep expertise in SystemVerilog or VHDL and familiarity with modern digital design flows
- Strong ability to diagnose and resolve complex design issues using scripting or programming such as Python and Tcl
- Demonstrated excellence in cross-functional leadership and communication across global teams
- Strong organisational skills with ability to manage multiple priorities in fast-paced environments
- Desirable: processor or accelerator microarchitecture experience
- Desirable: high-speed serial interfaces and complex, high-bandwidth IP blocks
- Desirable: arithmetic pipeline design and floating-point datapaths
- Desirable: advanced synthesis, timing analysis, power analysis and logical equivalence checking
- Desirable: design-for-test methodologies
- Desirable: power integrity and silicon device-level understanding
- Desirable: silicon bring-up and post-silicon validation experience
- Desirable: program planning and multi-project execution leadership