IP Design Verification Lead
We are looking for an IP Design Verification Lead for our team in Haifa to drive verification for next-generation PHY IPs at Apple. The PHY DV team operates at the intersection of verification, research, and innovation, continuously improving techniques, models, and flows to increase the efficiency and quality of PHY verification. This is a hands-on technical leadership role, combining deep verification expertise with team leadership and close collaboration with design, architecture, firmware, and system teams.
Lead the verification team, including hiring, planning, and communication with management. Strong teamwork and communication skills.
Minimum Qualifications
- BSc in Electrical Engineering
- 8+ years of industry experience, including verification team leadership
- Strong DV background with testbench development
- Experience with low-power verification, formal, FW verification, or emulation is a plus
- Proficiency in SystemVerilog and UVM
- Ability to lead teams to high-quality outcomes
- Define verification architecture and lead for execution
- Own verification methodologies, standards, and best practices across the team
- Drive improvements in verification flows and methodologies
- Collaborate closely with design teams on specifications, architecture, test plans, and testbench development
Preferred Qualifications
- MSc in Electrical Engineering