Physical Design Engineer (Staff / Sr. Staff / Principal)

Drive physical implementation and sign-off of critical blocks for next-generation AI and high-performance computing silicon, owning complex designs from RTL to GDSII across synthesis, floorplanning, place and route, clock tree synthesis, timing closure, extraction, physical verification, EM/IR, and final sign-off.

Responsibilities

• Own critical design blocks from RTL to GDSII through synthesis, floorplanning, place and route, timing closure, and sign-off.
• Implement and optimize floorplans, power plans, placement, clock tree synthesis, routing, extraction, and sign-off closure.
• Drive timing convergence across multiple modes and corners while meeting performance, power, area, and schedule goals.
• Evaluate microarchitecture tradeoffs with RTL and architecture teams.
• Develop physical design methodologies, implementation recipes, and automation flows.
• Perform synthesis, placement optimization, CTS, routing, timing ECOs, physical ECOs, extraction, and sign-off.
• Resolve timing, congestion, clocking, signal integrity, power integrity, and physical verification issues.
• Perform DRC, LVS, ERC, antenna, density, metal fill, and layout quality checks.
• Drive EM/IR analysis and power delivery sign-off.
• Create scripts to automate physical design tasks.
• Collaborate with RTL, DFT, STA, verification, CAD, packaging, and product engineering teams.
• Provide technical leadership and mentor engineers.

Requirements

• 8+ years of hands-on experience in physical design implementation and sign-off.
• Experience delivering high-performance blocks from RTL to GDSII in advanced technology nodes.
• Experience closing CPU, GPU, VPU, memory controller, DDR, NoC, AI accelerator, or other compute-intensive blocks.
• Expertise in synthesis, floorplanning, placement, CTS, routing, extraction, timing closure, and physical sign-off.
• Expertise in static timing analysis, timing constraints, clocking methodologies, multi-corner multi-mode closure, and timing ECO implementation.
• Experience with Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Calibre, or Apache RedHawk.
• Experience with advanced process technologies, preferably sub-5nm nodes.
• Understanding of power planning, IR drop, electromigration, signal integrity, congestion analysis, and physical design quality checks.
• Strong scripting skills in Tcl, Perl, or Python.
• Experience with low-power implementation, UPF, DFT, package-aware implementation, or hierarchical design.
• Strong analytical, problem-solving, communication, and technical leadership skills.

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements
• Professional development opportunities