Senior Physical Design Engineer
Execute physical implementation of high-speed PCIe IP and subsystems for an AI chip, owning the physical design flow from netlist to GDSII and collaborating with circuit design, DFT, and verification teams.
Responsibilities
- Own end-to-end physical design flow including floorplanning, placement, CTS, routing, STA, physical verification, and signoff for PCIe controller and PHY blocks.
- Perform timing closure for high-speed PCIe Gen 4/5/6 interfaces across PVT corners.
- Drive power integrity analysis including IR drop and electromigration across the power delivery network.
- Achieve DRC, LVS, and ERC physical verification closure using Calibre.
- Work with RTL and synthesis teams on logic restructuring for timing and area improvement.
- Contribute to PD methodology, scripts, and flow automation using Perl and Tcl.
- Support tapeout activities including GDS merge, fill insertion, and signoff checks.
Requirements
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of hands-on physical design experience in advanced TSMC process nodes; N6 and below preferred.
- Strong knowledge of PCIe protocol and high-speed interface physical design constraints.
- Strong hands-on CTS experience including skew balancing, useful skew, and multi-corner CTS closure.
- Proficiency with Cadence Innovus, Synopsys Primetime, and Tweaker.
- Experience resolving chip-level DRC, LVS, and EMIR issues for advanced nodes.
- Tapeout experience required.
- Experience with multi-die packaging, thermal/IR/EM signoff, signal integrity, DFT-aware physical design, or scripting is a plus.
Benefits
- Training and mentoring opportunities.
- Attractive welfare benefits.
- Inclusive environment with open workspaces and startup spirit.
- Opportunity to contribute directly to digital asset industry projects.
- Personal accountability, autonomy, growth, and learning opportunities.