CPU Digital Front‑end Design Engineer

Job Description:

1. Responsible for micro-architecture design and RTL implementation of high-performance CPU front-end pipeline, including instruction fetch, branch prediction, instruction decode, dispatch and instruction queue modules.

2. Complete detailed module design, state machine definition and logic development, and deliver high-quality Verilog/SystemVerilog RTL code according to architecture specifications.

3. Design pipeline hazard detection, dependency resolution, conflict handling and out-of-order scheduling logic to ensure stable, efficient and deadlock-free pipeline operation.

4. Conduct PPA (Performance, Power, Area) optimization, continuously improve instruction throughput, branch prediction accuracy and pipeline latency.

5. Collaborate with verification teams for module-level and system-level verification, analyze and fix functional bugs and corner-case issues.

6. Support SoC system integration and cross-module co-debug with execution backend and memory subsystem, and complete pre-tapeout optimization.

7. Deliver complete design documents and participate in architecture review and technical discussion.

Job Requirements:

1. Bachelor’s degree or above in Microelectronics, Computer Architecture, Electrical Engineering or related disciplines.

2. 3+ years of RTL design experience in CPU or high-performance SoC front-end development, proficient in Verilog/SystemVerilog.

3. Deep understanding of CPU front-end pipeline architecture, familiar with instruction fetch, branch prediction, decode pipeline, hazard detection and dependency resolution.

4. Familiar with RISC-V / ARM instruction set and CPU microarchitecture design; real chip tape-out experience is preferred.

5. Solid foundation in digital logic, timing closure and pipeline design, with clear understanding of PPA optimization methodologies.

6. Strong debugging skills, technical documentation ability and cross-team collaboration capability.