GPU Digital Frontend Design Engineer
Summary
Design GPU and AI accelerator chips as a digital frontend engineer: define microarchitecture, write synthesizable Verilog/SystemVerilog RTL for modules like SIMD Core and Tensor Core, optimize PPA, and collaborate on UVM verification, synthesis, and post-silicon debug.
Job Responsibilities
- Responsible for requirement analysis, GPU microarchitecture definition, specification drafting and module interface design for high-performance GPU/AI accelerator chips.
- Conduct RTL design and PPA optimization for GPU key modules including SIMD Core, Tensor Core, scheduling system, on-chip memory and interconnect network.
- Develop synthesizable Verilog/SystemVerilog code and optimize timing, area and power consumption.
- Collaborate with verification team on UVM verification plan, environment setup and debug.
- Work with algorithm and software teams for operator performance analysis and architecture optimization.
- Support logic synthesis, STA, low-power design, physical design co-optimization, FPGA prototyping and post-silicon debug.
Job Requirements
- Master’s degree or above in Microelectronics, Electronic Engineering, Computer Science or related fields.
- 2+ years digital IC frontend design experience; GPU / AI accelerator chip project experience is highly preferred.
- Proficient in Verilog/System Verilog; familiar with Python / Tcl / Perl scripting.
- Solid understanding of GPU/SoC architecture and low-power design methodology.
- Hands-on experience with IC frontend flow and EDA tools: DC, PT, Verdi, Spyglass, LEC.