Principal/Staff Design Verification Engineer

Lead verification strategy and execution for complex IC designs, ensuring robust functional coverage and high-quality silicon through advanced verification methodologies, automation, and collaboration with design and architecture teams.

Responsibilities

• Lead verification strategy and execution for assigned DUT blocks.
• Guide and mentor verification engineers in developing and maintaining verification test plans.
• Develop verification environments, testbenches, and test sequences.
• Create test patterns and stimulus scenarios for DUT functionality and corner cases.
• Run simulations, analyze results, and debug RTL issues with design engineers.
• Manage regression testing across feature updates and bug fixes.
• Track and improve functional and code coverage metrics for sign-off readiness.
• Document test cases, results, coverage reports, and verification sign-off.
• Develop automation scripts, reusable verification components, and VIP.
• Collaborate with design, architecture, and physical implementation teams.
• Mentor junior team members.

Requirements

• At least 10 years of relevant experience in IC/SoC functional verification.
• Strong debugging skills with RTL simulation and waveform analysis tools.
• Proficiency in UVM, SystemVerilog, Verilog, and SVA.
• Strong knowledge of AXI, NoC, and RISC-V protocols.
• Proven ability to lead verification efforts and mentor engineers.
• Strong communication and collaboration skills.
• Bachelor’s degree or above in Microelectronics, Semiconductor Engineering, Electronic and Electrical Engineering, or a related field.

Benefits

• Attractive welfare benefits.
• Training and mentoring.
• Inclusive and diverse work environment.
• Opportunities to contribute to digital asset industry projects.
• Personal accountability, autonomy, growth, and learning opportunities.