Senior Staff Front-End Engineer RTL Design

Design ASIC microarchitectures using Verilog HDL, conduct design reviews, integrate intellectual property, collaborate with verification and emulation teams, and close designs through synthesis, timing, and power analysis.

Responsibilities

• Participate in architectural design discussions
• Design and implement microarchitectures using Verilog HDL
• Conduct design reviews and control delivery quality
• Identify, select, and integrate soft and hard IP
• Collaborate with verification and emulation teams on test plans and debugging
• Collaborate with implementation teams on synthesis, timing, and power closure

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 3 to 5 years of RTL design experience on ASICs with tape-out experience
• Familiarity with industrial-standard RTL design and delivery flows
• Strong understanding of computer architecture and VLSI design
• Experience designing GPGPU, NPU, or CPU modules

Benefits

• Authentic and diverse workplace culture
• Inclusive environment with open workspaces and startup spirit
• Opportunity to network with industry pioneers
• Ability to contribute to the digital asset industry
• Involvement in new projects and process development
• Personal accountability, autonomy, growth, and learning opportunities
• Training, mentoring, welfare benefits, and developmental opportunities